A significant paradigm shift in design methodology is taking place with RTL design handoff. Shrinking process nodes, increasing SoC design complexities, and tightened purse strings have made the ...

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...

Synopsys is celebrating its 25th anniversary this year. This also means that availability of commercial logic synthesis is turning 25 years old. This paper looks at the history of logic ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

This solution provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process. Front-end designers can access digital design analysis and ...

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...

Rising design complexity causes innumerable headaches in achieving functional design closure. Startup firm Blue Pearl Software plans to address design closure at RTL using a combination of design-rule ...

Siemens Digital Industries Software has unveiled the Tessent RTL Pro, a software solution developed to help integrated circuit (IC) design teams streamline and accelerate a broad array of critical ...

The standard approach for testing IC logic is the use of scan chains, with embedded compression as the standard approach for applying scan patterns. Embedded compression enables the same test quality ...